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Silicon Labs /Series1 /EFR32FG12P /EFR32FG12P431F1024GM48 /IDAC0 /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (CURSINK)CURSINK 0 (MINOUTTRANS)MINOUTTRANS 0 (APORTOUTEN)APORTOUTEN 0APORTOUTSEL0 (PWRSEL)PWRSEL 0 (EM2DELAY)EM2DELAY 0 (APORTMASTERDIS)APORTMASTERDIS 0 (APORTOUTENPRS)APORTOUTENPRS 0 (MAINOUTEN)MAINOUTEN 0 (MAINOUTENPRS)MAINOUTENPRS 0 (PRSCH0)PRSSEL

PRSSEL=PRSCH0

Description

Control Register

Fields

EN

Current DAC Enable
CURSINK

Current Sink Enable
MINOUTTRANS

Minimum Output Transition Enable
APORTOUTEN

APORT Output Enable
APORTOUTSEL

APORT Output Select

32 (APORT1XCH0): APORT1X Channel 0

33 (APORT1YCH1): APORT1Y Channel 1

34 (APORT1XCH2): APORT1X Channel 2

35 (APORT1YCH3): APORT1Y Channel 3

36 (APORT1XCH4): APORT1X Channel 4

37 (APORT1YCH5): APORT1Y Channel 5

38 (APORT1XCH6): APORT1X Channel 6

39 (APORT1YCH7): APORT1Y Channel 7

40 (APORT1XCH8): APORT1X Channel 8

41 (APORT1YCH9): APORT1Y Channel 9

42 (APORT1XCH10): APORT1X Channel 10

43 (APORT1YCH11): APORT1Y Channel 11

44 (APORT1XCH12): APORT1X Channel 12

45 (APORT1YCH13): APORT1Y Channel 13

46 (APORT1XCH14): APORT1X Channel 14

47 (APORT1YCH15): APORT1Y Channel 15

48 (APORT1XCH16): APORT1X Channel 16

49 (APORT1YCH17): APORT1Y Channel 17

50 (APORT1XCH18): APORT1X Channel 18

51 (APORT1YCH19): APORT1Y Channel 19

52 (APORT1XCH20): APORT1X Channel 20

53 (APORT1YCH21): APORT1Y Channel 21

54 (APORT1XCH22): APORT1X Channel 22

55 (APORT1YCH23): APORT1Y Channel 23

56 (APORT1XCH24): APORT1X Channel 24

57 (APORT1YCH25): APORT1Y Channel 25

58 (APORT1XCH26): APORT1X Channel 26

59 (APORT1YCH27): APORT1Y Channel 27

60 (APORT1XCH28): APORT1X Channel 28

61 (APORT1YCH29): APORT1Y Channel 29

62 (APORT1XCH30): APORT1X Channel 30

63 (APORT1YCH31): APORT1Y Channel 31
PWRSEL

Power Select
EM2DELAY

EM2 Delay
APORTMASTERDIS

APORT Bus Master Disable
APORTOUTENPRS

PRS Controlled APORT Output Enable
MAINOUTEN

Output Enable
MAINOUTENPRS

PRS Controlled Main Pad Output Enable
PRSSEL

IDAC Output Enable PRS Channel Select

0 (PRSCH0): PRS Channel 0 selected.

1 (PRSCH1): PRS Channel 1 selected.

2 (PRSCH2): PRS Channel 2 selected.

3 (PRSCH3): PRS Channel 3 selected.

4 (PRSCH4): PRS Channel 4 selected.

5 (PRSCH5): PRS Channel 5 selected.

6 (PRSCH6): PRS Channel 6 selected.

7 (PRSCH7): PRS Channel 7 selected.

8 (PRSCH8): PRS Channel 8 selected.

9 (PRSCH9): PRS Channel 9 selected.

10 (PRSCH10): PRS Channel 10 selected.

11 (PRSCH11): PRS Channel 11 selected.

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data